In the application of power transistor, the overall size and thermal dissipation of the final semiconductor device are two important parameters. The thermal performance of the device is improved by exposing part of the electrode of the transistor, but such process is often difficult to control, and the heat dissipation is still poor. FIG. 1A is a conventional DirectFET package, which is disclosed in “DirectFET Technology—Board Mounting Application Note” January 2002—International Rectifier. Such packages are suitable for industrial applications that require extremely low conduction resistance RDSon, such as high-power DC motors, DC/AC inverter, as well as dynamic ORing hot-swap, electrical fuses and other high current switching applications. As shown in FIGS. 1A-1B, the DirectFET package includes a metal can 10 with the leads 10a and 10b extended horizontally at two opposite edges. A MOSFET 11 is mounted in the metal can 10, where a drain electrode at the back of the MOSFET 11 is directly attached to the metal can 10, while the top surfaces of the source electrode 11a and the gate electrode 11b on the front of the MOSFET 11 are coplanar with the top surfaces of the leads 10a, 10b of the metal can 10. Thus the source electrode 11a, gate electrode 11b, and two leads 10a and 10b can all be mounted simultaneously on the contact pads on the PCB. The DirectFET package generally has a thickness of less than 0.7 mm, thus provide an ideal solution for the compact-size power supply design in high-power industries.
FIGS. 2A-2B illustrate a conventional X-FET semiconductor package. FIG. 2A is a schematic of the lead frame 20 having a die pad 20b with two leads 20a extended horizontally at two opposite edges of the die pad 20b, where the plane of the leads 20a is higher than the plane of the die pad 20b. As shown in FIG. 2B, the bottom electrode of a MOSFET is attached on the die pad 20b, while the top surface of the source electrode 21a and the gate electrode 21b on top of the MOSFET are coplanar with the upper surface of the leads 20a. In FIG. 2B, after the molding is completed, the MOSFET is completely covered by molding layer 25 while the source electrode 21a, the gate electrode 21b and the top surface of the leads 20a are exposed from the molding layer 25 as the electrode terminals.
As shown in FIGS. 1A-1B and 2A-2B, leads 10a, 10b and 20a are on opposite sides of the chip, which results in a larger package size. Furthermore, to satisfy the coplanar condition of the source and gate electrodes at the front of the chip and the top surface of the leads, the thickness of the MOSFET needs to be precisely controlled within a very narrow range, which is a great challenge to the equipment accuracy as well as cost control. In addition, in the package of FIG. 2B, the top surface of the lead 20a is plated with a metallic layer while the gate electrode 21b and the source electrode 21a is protected by a tape that can be peeled after plating is done, as such the manufacturing process is more complicated.
It is within this context that embodiments of the present invention arise.